MIT designs new photonic chips that are 10 million times more efficient than electronic ones
Researchers at the Massachusetts Institute of Technology (MIT) have developed a new type of "photon" chip that uses light instead of electricity and consumes relatively little power in the process. The chip is used to process large-scale neural networks millions of times more efficiently than existing computers. The simulation results show that the efficiency of photonic chip running optical neural network is 10 million times that of electronic chip.
Neural networks are a machine learning model widely used for tasks such as robot target recognition, natural language processing, drug development, medical imaging and driving driverless cars. New optical neural networks that use optical phenomena to accelerate calculations can operate faster and more efficiently than other electronic counterparts.
However, with the increasing complexity of traditional neural networks and optical neural networks, they consume a lot of energy. To solve this problem, researchers and major tech companies including Google, IBM and Tesla have developed "artificial intelligence accelerators," specialized chips that increase the speed and efficiency of training and testing neural networks.
For electronic chips, including most AI accelerators, there is a theoretical minimum energy consumption limit. Recently, researchers at MIT began developing photon accelerators for optical neural networks. These chips perform orders of magnitude more efficiently, but they rely on some bulky optical components that limit their use in relatively small neural networks.
In a paper published in Physical Review X, MIT researchers describe a new type of photon accelerator that uses more compact optics and optical signal processing to dramatically reduce power consumption and chip area. This allows chips to scale to neural networks, several orders of magnitude larger than their counterparts.
It is more than 10 million times lower than the energy consumption limit of the traditional electron accelerator
The simulation training of the neural network on the MNIST image classification data set shows that the accelerator can theoretically handle the neural network, and the energy consumption limit is more than 10 million times lower than that of the traditional electron accelerator, and about 1000 times lower than that of the photon accelerator. The researchers are now working on a prototype chip to test the results.
"People are looking for a technology that can calculate beyond the basic energy limits," says Ryan Hamerly, a postdoctoral fellow at the Electronics Research Laboratory. "Photon accelerators are promising... But our motivation is to build a [photon accelerator] that can scale to large neural networks."
Practical applications of these technologies include reducing energy consumption in data centers. "There is an increasing need for data centers running large neural networks, and as the demand grows, it becomes more difficult to compute," says co-author Alexander Sludds, a graduate student at the Electronics Research Lab. The aim is to "leverage neural network hardware for computing needs... To solve the bottleneck of energy consumption and delay."
Co-authors of the paper with Sludds and Hamerly: Liane Bernstein, a graduate student at RLE and co-author; Marin Soljacic, professor of physics at MIT; Dirk Englund, an associate professor of electrical engineering and computer science at MIT; A researcher at RLE, and the head of the Quantum Photonics Laboratory.
Relies on a more compact, energy-efficient "optoelectronic" solution
Neural networks process data through many layers of computing containing interconnected nodes called "neurons" to find patterns in the data. The neuron receives input from its upstream "neighbor" and computes an output signal, which is sent to a neuron farther downstream. Each input is also assigned a "weight," a value based on its relative importance to all other inputs. As data spreads "deeper" through the layers, the network gradually learns more complex information. Finally, the output layer generates predictions based on the calculations of the entire layer.
The goal of all AI accelerators is to reduce the amount of energy required to process and move data in a particular linear algebra step in a neural network, called "matrix multiplication." There, neurons and weights are encoded into separate rows and lists, which are then combined to calculate the output.
In a conventional photon accelerator, a pulsed laser encodes information about each neuron in a layer, then flows into a waveguide and through a beam splitter. The resulting optical signal is fed into a grid of square optical elements called a "Mach-Zehnder interferometer", which is programmed to perform matrix multiplication. The interferometer is encoded with information about each weight, and uses signal interference techniques that process optical signals and weight values to calculate the output of each neuron. But there is a scaling problem: for each neuron, there must be a waveguide, and for each weight, there must be an interferometer. Because the amount of weight is proportional to the number of neurons, those interferometers take up a lot of space.
"You quickly realize that the number of input neurons will never exceed 100 or so, because you can't fit that many components on the chip," Hamerly says. "If your photon accelerator can't handle more than 100 neurons per layer, it's hard to apply large neural networks to this kind of structure."
The researchers' chip relies on a more compact, energy-efficient "optoelectronic" scheme that encodes the data using optical signals but uses "balanced zero-difference detection" for matrix multiplication. This is a technique that produces a measurable electrical signal by calculating the product of the amplitudes (wave heights) of two optical signals.
The information encoded by the light pulses goes in and out of each neural network layer of neurons -- used to train the network -- flowing through a single channel. Separate pulses encoded with the weight information of the entire row in the matrix multiplication table flow through separate channels. An optical signal that transmits neuron and weight data to a grid of zero-error photodetectors. The photodetector uses the amplitude of the signal to calculate the output value of each neuron. Each detector feeds the electrical output of each neuron into a modulator, which converts the signal back into a pulse of light. The optical signal becomes the input to the next layer, and so on.
This design requires only one channel per input and output neuron, and only as many zero-error photodetectors as neurons, without weight. Because the number of neurons is always far less than the weight, which saves a lot of space, the chip is able to scale to neural networks with more than a million neurons per layer.
Find ******
With photon accelerators, there is inevitable noise in the signal. The more light that is injected into the chip, the less noise it makes and the more accurate it becomes -- but it becomes very inefficient. The less input light, the higher the efficiency, but it will have a negative impact on the performance of the neural network. But there is a "****** point," Bernstein says, that uses minimal optical power while maintaining accuracy.
The ****** position of the AI accelerator is measured by how many joules it takes to perform a single operation that multiplies two numbers at a time, such as matrix multiplication. Nowadays, traditional accelerators are measured in picojoules or quadrillion joule. Photon accelerators, measured in attojoules, are a million times more efficient.
In simulations, the researchers found that their photon accelerator could operate at a lower efficiency than attojoules. "You can send some minimal optical power before you lose accuracy. The basic limitations of our chip are much lower than those of traditional accelerators...... And lower than other photon accelerators, "Bernstein said.